The present application relates to semiconductor processing, and more particularly to a method for forming semiconductor fins with self-aligned customization utilizing a graphoepitaxy directed self-assembly process.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (finFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Semiconductor fin field effect transistors (FETs) can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs. In finFET devices, a functional gate structure straddles a semiconductor fin.
Advanced technology node requires both high density semiconductor fins and precise customization capability. High density, e.g., sub 30 nm pitch, line/space arrays can be achieved by utilizing multiple sidewall image transfer (SIT) processes or directed self-assembly (DSA). However, based on the state of the art lithography tools and materials, removing one single line from the array without damaging the adjacent fin structure is extremely difficult due to the limitation from critical dimension uniformity, overlay and line-edge roughness.
In view of the above, there is a continued need for providing customized, high density semiconductor fins that overcomes the problems associated with prior art multiple sidewall image transfer processes and directed self-assembly processes.